OBJECTIVES OF SMDP-II PROJECT
Primary Objective - To train special manpower in the area of VLSI Design and related software at M.E./M.Tech level (Type-II manpower). In addition to this, generation of Type-III manpower i.e. M.E./M.Tech in other areas of electronics etc. with at least two courses on VLSI design will also be undertaken.
Secondary Objective - To train Type-IV manpower i.e. B.E./B.Tech in electronics etc. with graduate level courses on VLSI Design. However, the programme will not only be limited to generation of Type-II, III & IV manpower but would endeavour to generate Ph.D in various aspects of VLSI design/microelectronics (Type-I manpower) manpower as well. The establishment of VLSI design laboratories at RCs would also strengthen their academic programme.
MAIN COMPONENTS OF SMDP-II
Establishing the VLSI Design laboratories in all PIs and RC's with the Electronic Design Automation environment drawn by the Working Group. CEERI Pilani would act as the nodal agency for the centralized procurement of all hardware and EDA tools that would be provided to each of the RC and PI in order to get pricing advantage as well as maintaining a uniform standard throughout the country. In addition to the EDA tool environment being provided to all RC's and PIs, RC's would be provided with miscellaneous capital equipment required by the respective institution to take care of its testing and other needs and PIs. The misc. capital equipment procurement would be done by the respective RC'sTraining of laboratory engineers and technicians. Hands-on training would be provided on the hardware & EDA tools.
Conducting Instruction Enhancement Programme (IEP) for training of the faculty of 25 PIs by seven Resource Centres. To start with, seven IEP topics would be selected from the list drawn up by the Working Group (Annexure-III). 25 IEP's would be conducted during the entire project duration by 7 RC's. In addition to these, 5 EDA tool administration IEP would be conducted by CEERI Pilani.
Generation of Manpower in VLSI design and related software at: B.E/B.Tech level (Type IV manpower) - M.E/M.Tech level in the areas of Electronics, Communications, Computer Science, Instrumentation etc. (Type III manpower) - M.E/M.Tech in VLSI design & Microelectronics (Type II manpower) The Working Group has developed a model curriculum/syllabus, which all the participating institutions would be encouraged to follow. - PhD in various aspects of VLSI design and related software (Type I manpower).
All the participating institutions would be provided with salary grant for 2 temporary faculties during the project period. The RC's would be provided with salary grant for research/project staff. Both RC's and PI's would also be provided with salary grant for a lab engineer. In addition to this, CEERI Pilani would be provided with salary grant for 2 project assistants to monitor lab infrastructure at all the RC's and PI's.
International Guest Faculty: To invite distinguished international guest faculty e.g. from IEEE Circuits & Systems Society (CAS) under its Distinguished Lecture Program (DLP), and others including eminent NRI's to conduct short-term courses at RC's in selected areas of VLSI design.
The Project Implementation Unit at DIT would act as a national repository, facilitation and demonstration center for all EDA tools and designs done at RC's and PI's.
India Chip Programme: Selected VLSI circuit designed at various RC's and PIs would be siliconised either at Semiconductor Complex Ltd. Mohali or through International mechanisms like MOSIS, CMP, EURO Practice etc.
National VLSI Website & Mirror Site: A website at a national center which would be mirrored at all RC's would be created. RCs would provide contents for the National VLSI website. This would house all latest and updated tools including public domain tools, courses and reference designs, which may be developed at any of the RC's and PI's. All the RC's & PI's would be able to download resources from these sites as and when required. CEERI Pilani would host and support a web site especially for EDA tool and hardware configuration/administration and other issues.
In order to encourage the element of research, faculty of PIs as well as students would be provided with financial support to attend national conferences in the area of VLSI design/microelectronic. Students and faculty of RC's and PI's would be supported to attend IEEE conference anywhere in the area of VLSI design provided the students/faculty has an accepted paper for oral lecture presentation.
Book grants and grant for furniture for the VLSI design laboratory would also be provided to all RC's and PIs.
Annual RC/PI Workshop would be organized both at regional and national level in which apart from the overall project review, awards would be provided to best M.Tech projects. ZOPP workshop(s).
Involving coordinators from all RC's, PI's and representative from PIU/DIT would also be organized.
LIST OF 7 RCs AND 25 PIs FOR SMDP-II
IIT Bombay | IIT Madras | IISC Bangalore |
NIT Surat | NIT Trichy | NIT Surathkal |
SGSIT Indore | NIT Warangal | PSG Technology |
NIT Bhopal | NIT Calicut | BEC Shibpur |
NIT Nagpur | ||
IIT Dehi | IIT Kanpur | IIT Kharagpur |
IIT Guwahati | BHUIT | NIT Silchar |
NIT Srinagar | IIT Roorkie | NIT Rourkela |
NIT Hamirpur HP | MNIT Allahabad | NIT Jamshedpur |
NIT Jalandhar | NIT Durgapur | Jadavpur University |
NIT Kurukshetra | ||
TIET Patiala | ||
MNIT Jaipur |
FOR MORE DETAILS
http://www.nith.ac.in/smdp/about.html
